NIMCET SERIES Computer-awareness
Computer Architecture
19 previous year questions.
Volume: 19 Ques
Yield: Medium
High-Yield Trend
4
2025 6
2024 8
2023 1
2022 Chapter Questions 19 MCQs
01
PYQ 2022
medium
computer-awareness ID: nimcet-2
If a processor clock is rated as 2500 million cycles per second, then its clock period is:
1
sec
2
sec
3
sec
4
None of the above
02
PYQ 2023
medium
computer-awareness ID: nimcet-2
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:
1
13 bits
2
20 bits
3
11 bits
4
15 bits
03
PYQ 2023
medium
computer-awareness ID: nimcet-2
Which of the following is true about Von Neumann architecture?
1
It has separate storage for input/output operations
2
It has a separate processing unit for data and instructions
3
It has separate memory for data and instructions
4
It has a single memory unit for both data and instructions
04
PYQ 2023
medium
computer-awareness ID: nimcet-2
The time required for fetching and execution of one machine instruction is
1
Delay time
2
CPU cycle
3
Real time
4
Seek time
05
PYQ 2023
medium
computer-awareness ID: nimcet-2
If a processor clock is rated as 2500 million cycles per second, then its clock period is
1
sec
2
sec
3
sec
4
sec
06
PYQ 2023
medium
computer-awareness ID: nimcet-2
Which of the following registers is used to keep track of address of memory location where the next instruction is located?
1
Program counter
2
Memory Address Register
3
Memory data register
4
Instruction counters
07
PYQ 2023
medium
computer-awareness ID: nimcet-2
The time required for fetching and execution of one machine instruction is
1
Delay time
2
CPU cycle
3
Real time
4
Seek time
08
PYQ 2023
medium
computer-awareness ID: nimcet-2
If a processor clock is rated as 2500 million cycles per second, then its clock period is
1
sec
2
sec
3
sec
4
sec
09
PYQ 2023
medium
computer-awareness ID: nimcet-2
Which of the following registers is used to keep track of address of memory location where the next instruction is located?
1
Program counter
2
Memory Address Register
3
Memory data register
4
Instruction counters
10
PYQ 2024
medium
computer-awareness ID: nimcet-2
Consider the following 4-bit binary numbers represented in the 2's complement form: 1101 and 0100. What would be the result when we add them?
1
0001 and an overflow
2
1001 and no overflow
3
1001 and an overflow
4
0001 and no overflow
11
PYQ 2024
medium
computer-awareness ID: nimcet-2
Which of the following interfaces perform the transfer of data between the memory and the I/O peripheral without involving the CPU?
1
Branch Interface
2
Serial Interface
3
DMA
4
DDA
12
PYQ 2024
medium
computer-awareness ID: nimcet-2
Which of the following components is used to establish a communication link between a CPU and the peripheral devices to transfer data?
1
Memory address register
2
Instruction register
3
Memory data register
4
Index register
13
PYQ 2024
medium
computer-awareness ID: nimcet-2
Which of the following do not affect CPU performance?
1
Cache size
2
Number of cores
3
Amount of RAM
4
Clock speed
14
PYQ 2024
medium
computer-awareness ID: nimcet-2
Cache memory functions as an intermediary between
1
RAM and ROM
2
CPU and RAM
3
CPU and Hard Disk
4
None of these
15
PYQ 2024
medium
computer-awareness ID: nimcet-2
Which of the following components is not a part of an instruction format in CPU processing?
1
Source operand
2
Register file
3
Destination operand
4
Opcode
16
PYQ 2025
medium
computer-awareness ID: nimcet-2
In the design of a control unit of a processor, two common approaches are used: hardware control and microprogrammed control. Consider the following statements:
I. Hardware control units are generally faster but more difficult to modify than microprogrammed control units.
II. In a horizontal microprogrammed control unit, each control signal has a separate bit in the control word.
III. Vertical microprogramming leads to longer control words but provides greater parallelism.
IV. Microprogrammed control units are typically easier to implement and modify than hardware control units.
1
I, II, and IV only
2
I, II, III, and IV
3
II, III, and IV only
4
I, III, and IV only
17
PYQ 2025
medium
computer-awareness ID: nimcet-2
Consider a system running under two types of workloads: (a) CPU-intensive jobs, (b) I/O-intensive jobs. Which of the following statements about the relative performance of Interrupt-driven I/O and Programmed I/O is correct?
1
Programmed I/O performs better for CPU-intensive jobs, while interrupt-driven I/O performs better for I/O-intensive jobs
2
Interrupt-driven I/O performs better in both CPU-intensive and I/O-intensive workloads because it always reduces CPU involvement
3
Interrupt-driven I/O performs better for CPU-intensive jobs by freeing the CPU, while programmed I/O performs better for I/O-intensive jobs due to tighter control
4
Programmed I/O performs better in both CPU-intensive and I/O-intensive workloads because it gives the CPU full control
18
PYQ 2025
medium
computer-awareness ID: nimcet-2
In an instruction execution pipeline, the earliest that the instruction TLB and data TLB can be accessed are:
1
Fetch stage and fetch stage respectively
2
Fetch stage and memory stage respectively
3
Memory stage and execute stage respectively
4
Memory stage and memory stage respectively
19
PYQ 2025
medium
computer-awareness ID: nimcet-2
Consider a system with a CPU having 6 registers and 32-bit instructions. The maximum possible size of the main memory is 512 KB (1K = 2^{10}). Each instruction takes two registers and one memory address as operands. Which one of the following correctly gives the maximum possible distinct instructions that can be there in the instruction set of the CPU?
1
128
2
256
3
64
4
1024